The present invention relates to a semiconductor device which comprises a conductive film formed extending over an element isolation region and an element region 11 and has in the element region 11 a capacitor structure comprised of a semiconductor substrate, an insulating layer, and the conductive layer and, more particularly, to a semiconductor device used for MOSFET or MOS capacitor.
FIG. 31 shows an example of the shape of a conventional MOS capacitor. FIG. 32 is a sectional view taken along the line XXXIIxe2x80x94XXXII in FIG. 31.
On a silicon substrate 10, an element isolating insulation film 12 having an STI (Shallow Trench Isolation) structure is formed. The element isolating insulation film 12 constitutes an element isolation region, defining an element region 11 in the silicon substrate 10. The element region 11 has a square shape which has four sides and four corners.
In the substrate 10 within the element region 11, there is formed a diffusion layer 13 which has the same conductivity type as that of the silicon substrate 10 and has an impurity concentration higher than that of the silicon substrate 10. Connected to the diffusion layer, 13 is a wiring 14 which is provided for setting a potential of the silicon substrate 10.
A silicon oxide film 15 is formed on the substrate 10 within the element region 11. Further, a conductive film 16 is formed on the element isolating insulation film 12 and on the silicon oxide film 15. The conductive film 16 is composed of a metal, a semi-conductor containing an impurity, or the like. The conductive film 16 is formed extending over the element separation region and the element region 11, and, in the element region 11, a capacitor structure is formed which is comprised of the silicon substrate 10, the silicon oxide film 15 and the conductive film 16. Further, the conductive film 16 covers three sides S1, S2, and S3 and two corners C1 and C2 of the element region 11.
An interlayer insulation film (such as a TEOS film or a BPSG film) 17 is formed on the conductive film 16. The wiring 14 and a wiring 18 are formed on the interlayer insulation film 17. The wiring 14 is connected to the diffusion layer 13 via a contact hole 19, and the wiring 18 is connected to the conductive film 16 via a contact hole 20.
In the MOS capacitor having the above-mentioned structure, the conductive film 16 covers three sides S1, S2, and S3 and two corners C1 and C2 of the element region 11. This is for assuring the maximum capacitor area even if a misalignment takes place when the patterning of the conductive film 16 is made.
However, such a structure has a disadvantage that, in case that a voltage is applied across the silicon substrate 10 and the conductive film 16, the electric field concentrates in the sides S1, S2, and S3 and corners C1 and C2 of the element region 11 covered by the conductive layer 16, when viewed in the plan view of FIG. 31, that is, in an end portion D of the element region 11 covered by the conductive film 16, when viewed in the sectional view of FIG. 32. In particular, in the corners C1 and C2 of the element region 11, this electric field concentration is noticeably caused.
The reason why electric field concentration noticeably occurs in the corners C1 and C2 of the element region 11 is that, at the corners C1 and C2 of the element region 11, the edges of the element region 11 are tapered when seen both in the plan view and in the sectional view, and these corners C1 and C2 are covered by the conductive film 16. This point will be described later in more detail in connection with the manufacturing method of the semiconductor device.
Further, if the electric field concentrates in the capacitor insulation film (silicon oxide film 15) of the MOS capacitor, at the corners C1 and C2 of the elements region 11, then breakdown becomes apt to occur in the capacitor insulation film, at the corners C1 and lowering the reliability and the manufacturing yield of semiconductor devices.
The method of manufacturing the MOS capacitor shown in FIG. 31 and FIG. 32 will be described below.
First, as shown in FIG. 33, a buffer silicon oxide film 21 is formed by thermal oxidation on the silicon substrate 10. Further, by the LPCVD method, a silicon nitride film 22 which functions as a mask material when CMP (chemical mechanical polishing) is performed is formed on the buffer silicon oxide film 21.
Next, as shown in FIG. 34, on the silicon nitride film 22, a resist pattern for defining the element isolation region and the element region 11 from each other is formed by a photolithography step, and, by performing anisotropic etch (such as RIE) using this resist pattern as a mask, the silicon nitride film 22, the buffer silicon oxide film 21 and the silicon substrate 10 are successively etched. As a result, in the substrate 10, there is formed a trench 23 which constitutes the element isolation region. After this, the resist pattern is removed.
Next, as shown in FIG. 35 and FIG. 36, a silicon oxide film is formed by the LPCVD method over the surface of the silicon substrate 10 so as to sufficiently fill up the trench 23. After this, by CMP, this silicon oxide film is polished under the condition that the silicon nitride film 22 is made to serve as a stopper. As a result, the silicon oxide film is left only in the trench 23, and thus, the element isolating insulation film 12 of STI structure is formed.
Next, as shown in FIG. 37 and FIG. 38, the silicon nitride film 22 which is a mask material is removed by hot phosphoric acid treatment. Further, by dilute hydrofluoric acid treatment, the buffer silicon oxide film 21 is removed.
Here, when the buffer silicon oxide film 21 is removed, the surface portion of the element isolating insulation film 12 comprised of a silicon oxide film is also etched. The element isolating insulation film 12, which is sufficiently thick as compared with the buffer silicon oxide film 21, is not all removed, however, particularly, the corner portions of the element region 11 are noticeably etched when seen in a plan view, or the element isolating insulation film 12 is noticeably etched in the end portion D of the element region 11 when seen in a sectional view, and thus, these portions are exposed.
The cause for the occurrence of such a phenomenon is considered to lie in the film quality (density) of the element isolating insulation film 12. That is, when the silicon oxide film is buried into the trench 23, the density of the silicon oxide film in the corner portions of the element region 11 become lower than that of the other portion in some cases, depending on the depositing condition of the CVD. In general, the etching rate of a silicon oxide film is larger in the low density portion than in the high density portion thereof, so that, particularly, the silicon oxide film in the corners of the element region 11 is noticeably etched, and thus, the corners of the element region 11 become apt to be exposed.
Next, as shown in FIG. 39 and FIG. 40, the silicon oxide film 15 is formed by thermal oxidation on the silicon substrate 10 in the element region 11.
Further, as shown in FIG. 41 and FIG. 42, a conductive film (such as a polycrystalline silicon film) 16 is formed by the LPCVD method on the element isolating insulation film 12 and on the silicon oxide film 15. A resist pattern is formed by photolithography, and, using this resist pattern as a mask, the conductive film 16 is patterned by anisotropic etching. After this, the resist pattern is removed off.
Here, the conductive film 16 covers the corners of the element region 11 through the silicon oxide film 15. Due to this, in case a voltage is applied between the silicon substrate 10 and the conductive film 16, the electric field concentrates in the portions of the silicon oxide film 15 which lie on the corners of the element region 11; and thus, breakdown is apt to be caused.
Next, as shown in FIG. 43, by the ion implantation method, an impurity having the same conductivity type as that of the silicon substrate 10 is implanted into the silicon substrate 10 to form a diffusion layer 13. In case the conductive film 16 is comprised of a polycrystalline silicon film, the impurity is introduced into the polycrystalline film by this ion implantation.
After this, by the LPCVD method, an interlayer insulation film (such as a silicon oxide film) 17 is formed over the surface of the silicon substrate 10, covering the conductive layer 16. Further, after a contact hole 19 reaching the diffusion layer 13 is formed in the interlayer insulation film 17, a wiring 14 is formed extending on the interlayer insulation film 17 and in the contact hole 19.
By the steps mentioned above, the MOS capacitor shown in FIG. 31 and FIG. 32 is completed.
In the case of the MOS capacitor formed by such a manufacturing method as mentioned above, the electric field is apt to concentrate on the silicon oxide film in the corners of the element region 11, due to which there arises the problem that breakdown takes place, and thus, the reliability and manufacturing yield of semiconductor devices are lowered.
FIG. 44 shows another example of the conventional MOS capacitor shape.
This shape of MOS capacitor is similar to the shape of the MOS capacitor explained in connection with foregoing Example 1. That is, on a silicon substrate 10, an element isolating insulation film (element isolation region) 12 is formed, and, on the element region 11 surrounded by the element isolating insulation film 12, a conductive film 16 is formed. The conductive film 16 covers three sides and two corners of the element region 11.
FIG. 45 shows an example of the shape of a conventional MOSFET.
On a silicon substrate 10, an element isolating insulation film (element isolation region) 12 is formed, and, on the element region 11 surrounded by the element isolating insulation film 12, a conductive film (gate electrode) 16 is formed through a gate insulation film. The element region 11 has a square shape, and the conductive film 16 extends in the direction perpendicular to two mutually opposed sides of the element region 11 in a state striding over the element region 11. Wirings 14a and 14b are connected to a source/drain diffusion layer via contact holes 19a and 19b, and a wiring 18 is connected to the conductive film 16 via a contact hole 20.
FIG. 46 shows another example of the conventional MOSFET shape.
In this example, the shape of the conductive film (gate electrode) 16 largely differs as compared with that in the example shown in FIG. 45. That is, in this example, the conductive film 16 is formed so as to cover a corner of the element region 11, whereby the transistor is reduced in size and miniaturized, and thus, the shape of the integrated circuit as a whole is reduced.
The MOS capacitor shown in FIG. 44 and the MOSFET shown in FIG. 46 are both alike laid out in such a manner as to cover corners of the element region 11. Such a shape results in making breakdown apt to be caused due to the electric field concentration in the insulation film (the capacitor insulation film or the gate insulation film) portions lying on the corners of the element region 11, so that the initial defect rate of semiconductor devices is increased, the useful life thereof is shortened, and in addition, the reliability and the manufacturing yield thereof are deteriorated.
The peculiar problematic points corresponding to the element isolation methods in the cases where shapes as mentioned above are adopted will be successively described.
(i) Element Isolation Method According to the LOCOS Method
First, as shown in FIG. 47, a buffer silicon oxide film 21 is formed on a silicon substrate 10 by thermal oxidation. Further, by the LPCVD method, a silicon nitride film 22 which functions as a mask material at the time of forming the element isolating insulation film is formed on the buffer silicon oxide film 21.
Further, by a photolithography step, a resist pattern 24 for partitioning the element isolation region and the element region 11 is formed on the silicon nitride film 22, and, by the use of this resist pattern 24 as a mask, the silicon nitride film 22 is etched by anisotropic etching (such as RIE).
After this, when the resist pattern 24 is removed, the pattern of the silicon nitride film 22 is formed as shown in FIG. 48.
Next, as shown in FIG. 49, the surface of the portion of the silicon substrate 10 which is not covered by the silicon nitride film 22 used as a mask material is oxidized by thermal oxidation to form an element isolating insulation film (field oxide film) 12. Thereafter, the silicon nitride film 22 is removed, and further, the buffer silicon oxide film 21 is removed by the use of a wet etchant such as NH4F, whereby, as shown in FIG. 50, the silicon substrate 10 is exposed in the element region 11 surrounded by the element isolating insulation film 12.
Next, as shown in FIG. 51, a silicon oxide film 15 is formed on the thus exposed silicon substrate 10 by thermal oxidation.
Further, as shown in FIG. 52, a conductive film (such as a polycrystalline silicon film) 16 is formed by the LPCVD method on the element isolating insulation film 12 and on the silicon oxide film 15. In case the conductive film 16 is comprised of a polycrystalline film, for example phosphorus (P) which is an n-type impurity is introduced into this polycrystalline silicon film.
Next, as shown in FIG. 53, a resist pattern is formed on the conductive film 16 by a photolithography step, and, using this resist pattern as a mask, the conductive film 16 is patterned by anisotropic etching (such as RIE). Thereafter, the resist pattern is removed, and a diffuses layer 13 is formed by the ion implantation method.
The problematic point of the element isolation method according to the LOCOS method lies in that, for example, when the silicon oxide film 15 which constitutes the gate insulation film of a MOSFET is formed, the portions of the silicon oxide film 15 which lie in the end portions (sides and corners) of the element region 11 becomes thinner than the portion of the silicon oxide film 15 which lies in the center portion of the element region 11.
This phenomenon results from the fact that the silicon oxide film (thermal oxide film) 15 is selectively formed on the exposed silicon substrate 10 (element region 11). That is, in the thermal oxidation of the silicon substrate 10, the thermal oxide film is expanded in volume, so that, in the end portions of the element region 11, the stress due to this volume expansion concentrates, retarding the oxidation speed. In particular, in the corners of the element region 11, large stress concentrates, and thus, the silicon oxide film 15 is noticeably thinned.
Further, due to such circumstances, those portions of the silicon oxide film 15 which lie in the corners of the element region 11 are poor in film quality and have a high defect density.
Thus, if the conducive film 16 is formed so as to cover the corners of the element region 11s, then, when a voltage is applied across the silicon substrate 10 and the conductive film 16, the electric field concentrates in the thin portions of the silicon oxide film 15 lying in the corner portions of the element region 11 and, as a result, leakage current is apt to be caused. Further, this leakage current results in increasing the initial defect rate of semiconductor devices and shortening the useful life thereof and, in addition, lowering the reliability and the manufacturing yield thereof.
(ii) Trench Element Isolation Method (STI) I
The trench element isolation method is superior in respect of the high degree of integration of elements and the flattening of the surface on the silicon substrate; and thus, this method is becoming the main stream of the recent element isolation.
First, as shown in FIG. 55, a buffer silicon oxide film 21 is formed on a silicon substrate 10 by thermal oxidation. Further, by the LPCVD method, a silicon nitride film 22 which functions as a mask material at the time of performing CMP is formed on the buffer silicon oxide film 21. By a photolithography step, a resist pattern 24 for partitioning the element isolation region and the element region 1110 is formed on the silicon nitride film 22, and, using this resist pattern 24 as a mask, the silicon nitride film 22, the buffer silicon oxide film 21 and the silicon substrate 10 are successively etched by RIE.
After this, the resist pattern 24 is removed, whereby, as shown in FIG. 56, a trench 23 which will constitute an element isolation region is formed in the silicon substrate 10.
Next, as shown in FIG. 57, a silicon oxide film 12xe2x80x2 which completely fills up the trench 23 is formed on the whole surface of the silicon substrate 10 by the LPCVD method or the plasma CVD method.
After this, the silicon oxide film 12xe2x80x2 is polished by CMP under the condition that the silicon nitride film 22 is used as a stopper, whereby, as shown in FIG. 58, the silicon oxide film 12xe2x80x2 is left only in the trench 23, and thus an element isolating insulation film 12 of STI structure is formed.
Further, the silicon nitride film 22 which is a mask material is removed by performing a measure such as RIE, CDE (Chemical Dry Etching), hot hydrofluoric acid treatment. Further, using for example HF, NH4F, the buffer silicon oxide film 21 is removed. In this case, the element isolation insulating film 12 is etched to such a degree that the surface thereof becomes approximately equal to the surface of the silicon substrate 10 as shown in FIG. 59.
Next, as shown in FIG. 60, a silicon oxide film 15 is formed by thermal oxidation on the silicon substrate 10 in the element region 11.
Further, as shown in FIG. 61, a conductive film (such as a polycrystalline silicon film) 16 is formed on the element isolating insulation film 12 and on the silicon oxide film 15 by the LPCVD method. By photolithography, a resist pattern is formed, and, using this resist pattern as a mask, the conductive film 16 is patterned by RIE. After this, the resist pattern is peeled off.
The problematic point of the trench element isolation method is that, when the buffer silicon oxide film 21 is removed, the surface of the element isolating insulation film (silicon oxide film) 12 becomes lower than the surface of the silicon substrate 10 in some cases. In this case, particularly if the conductive film 16 is formed so a as to cover corners of the element region 11, then, when a voltage is applied across the silicon substrate 10 and the conductive film 16, the electric field concentrates in the portions of the silicon oxide film 15 which lie on the corner portions of the element region 11, and thus, there occurs a state in which breakdown is apt to be caused.
Thus, there arises the problem that the MOS capacitors and MOSFETs formed by such a manufacturing method are low in the reliability and the manufacturing yield.
(iii) Trench Element Isolation Method (STI) II
This trench element isolation method has its feature in the point that, for example, after the gate insulation film of a MOSFET is formed, the element isolating insulation film is formed.
First, as shown in FIG. 62, a silicon oxide film (gate insulation film) 15 is formed on a silicon substrate 10 by thermal oxidation. Further, by the LPCVD method, a conductive film (such as a polycrystalline film) 16A and a silicon oxide film 22 which functions as a mask material at the time of performing CMP are formed on the silicon oxide film 15. By a photolithography step, a resist pattern 24 for partitioning the element isolation region and the element region 11 is formed on the silicon nitride film 22, and, using this resist pattern 24 as a mask, the silicon nitride film 22, the conducive film 16A, the silicon oxide film 15 and the silicon substrate 10 are successively etched by RIE.
After this, the resist pattern 24 is removed, whereby, as shown in FIG. 63, a trench 23 which will constitute the element isolation region is formed in the silicon substrate 10.
Next, as shown in FIG. 64, a silicon oxide film 12xe2x80x2 for completely filling up the trench 23 is formed on the whole surface of the silicon substrate 10 by the LPCVD method or the plasma CVD method.
After this, by CMP, the silicon oxide film 12xe2x80x2 is polished under the condition that the silicon nitride film 22 is serves as a stopper, whereby, as shown in FIG. 65, the silicon oxide film 12xe2x80x2 is left only in the trench 23, and thus, an element isolating insulation film 12 of STI structure is formed.
Next, as shown in FIG. 66, the element isolating insulation film 12 is etched by the use of, for example, HF, NH4F, whereby the surface of the element isolating insulation film 12 is brought close to the surface of the conductive film 16A. By so doing, the difference in height between the element isolating insulation film 12 and the conductive film 16A is reduced, so that, when a conductive film (gate electrode) is processed later, a sufficient processing margin can be secured.
After this, by a measure such as RIE, CDE or hot phosphoric acid treatment, the silicon nitride film 22 which is a mask material is removed, whereby a structure as shown in FIG. 67 can be obtained.
Next, as shown in FIG. 68, the natural oxide film existing on the surface of the conductive film 16A is removed, and then, by the LPCVD method, a conductive film (such as a polycrystalline silicon film) 16B is formed in a state stacked on the conductive film 16A. Further, by photolithography, a resist pattern is formed, so that, using this resist pattern as a mask, the conductive film (gate electrode) 16B is patterned by RIE. After this, the resist pattern is peeled off.
The problematic point of this trench element isolation method lies in that, for example when the surface of the element isolating insulation film 12 is etched by the use of, for example, HF, NH4F, if the element isolating insulation film 12 and the silicon nitride film 22 are not so tightly joined to each other, then the etching proceeds along the interface between the element isolating insulation film 12 and the silicon nitride film 22, as a result of which the silicon oxide film (gate insulation film) 15 comes to be etched.
Particularly, in the corner portions of the element region 11, the shape thereof is apt to become unstable, so that such a phenomenon is apt to take place. Thus, if the conductive films 16A and 16B are formed so as to cover corners of the element region 11, then there arise problems such as the problem that, in case a voltage is applied across the silicon substrate 10 and the conductive films 16A and 16B, breakdown takes place, or the occurrence frequency of initial defects of semiconductor devices is increased, and thus, the useful life of the semiconductor devices is shortened.
The present invention has been made in order to give solutions to the above-mentioned problems, and it is the object of the invention to prevent the occurrence of breakdown and enhance the reliability and manufacturing yield with respect to a semiconductor device such as MOSFET or MOS capacitor which comprises a conducive film formed extending over an element isolation region and an element region and has, in the element region, a capacitor structure comprising a semiconductor substrate, an insulation layer and a conductive film.
In order to achieve the above-mentioned object, according to a first aspect of the present invention, there is provided a semiconductor device comprising an element region having a polygonal shape which has a plurality of sides and a plurality of corners; an element isolation region surrounding the element region; an insulation film formed on the element region; and a conductive film formed on the insulation film, having such a shape as to cover two adjacent sides of the element region and not to cover a corner which is an intersecting point of the two adjacent sides of the element region.
In a semiconductor device according to the first aspect of the present invention, the shape of the element region may be square.
In a semiconductor device according to the first aspect of the present invention, the shape of the element region may be rectangular.
In a semiconductor device according to the first aspect of the present invention, the shape of the element region may be of L-shape.
In a semiconductor device according to the first aspect of the present invention, the shape of the element region may be convex.
In a semiconductor device according to the first aspect of the present invention, the element isolation region may have a LOCOS structure.
In a semiconductor device according to the first aspect of the present invention, the element isolation region may have an STI structure.
In a semiconductor device according to the first aspect of the present invention, the conductive film may be an electrode of a MOS capacitor.
In a semiconductor device according to the first aspect of the present invention, the conductive film may be a gate electrode of a MOSFET.
According to a second aspect of the present invention, there is provided a semiconductor device comprising an element region having a ring shape which has a plurality of sides and a plurality of corners; an element isolation region surrounding the element region; an insulation film formed on the element region; and a conductive film formed on the insulation film, having such a shape as to cover two adjacent sides inside the ring shape and not to cover a corner which is an intersecting point of the two sides inside the ring shape, wherein the element region has a ring shape which has a plurality of sides and a plurality of corners, the conductive film has such a shape as to cover two adjacent sides and not to cover the corner which is the intersecting point of the two adjacent sides inside the ring shape.
In a semiconductor device according to the second aspect of the present invention, the shape of the element region may be square-like ring.
In a semiconductor device according to the second aspect of the present invention, the shape of the element region may be rectangle-like ring.
In a semiconductor device according to the second aspect of the present invention, the element isolation region may have a LOCOS structure.
In a semiconductor device according to the second aspect of the present invention, the element isolation region may have an STI structure.
In a semiconductor device according to the second aspect of the present invention, the conductive film may be an electrode of a MOS capacitor.
In a semiconductor device according to the second aspect of the present invention, the conductive film may be a gate electrode of a MOSFET.
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit comprising a semiconductor substrate and a plurality of semiconductor elements formed on the semiconductor substrate, each of the semiconductor elements including an element region having a polygonal shape which has a plurality of sides and a plurality of corners; an element isolation region surrounding the element region; an insulation film formed on the element region; and a conductive film formed on the insulation film, having such a shape as to cover two adjacent sides of the element region and not to cover a corner which is an intersecting point of the two adjacent sides of the element region.
In a semiconductor device according to the third aspect of the present invention, the shape of the element region may be square.
In a semiconductor device according to the third aspect of the present invention, the shape of the element region may be rectangular.
In a semiconductor device according to the third aspect of the present invention, the shape of the element region may be of L-shape.
In a semiconductor device according to the third aspect of the present invention, the shape of the element region may be convex.
In a semiconductor device according to the third aspects of the present invention, the element isolation region may have a LOCOS structure.
In a semiconductor device according to the third aspect of the present invention, the element isolation region may have an STI structure.
In a semiconductor device according to the third aspect of the present invention, the conductive film may be an electrode of a MOS capacitor.
In a semiconductor device according to the third aspect of the present invention, the conductive film may be a gate electrode of a MOSFET.
In a semiconductor device according to the third aspect of the present invention, the element regions may be arranged in a matrix form.
According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit comprising a semiconductor substrate and a plurality of semiconductor elements formed on the semiconductor substrate, each of the semiconductor elements including an element region having a ring shape which has a plurality of sides and a plurality of corners; an element isolation region surrounding the element region; an insulation film formed on the element region; and a conductive film formed on the insulation film, having such a shape as to cover two adjacent sides inside the ring shape and not to cover a corner which is an intersecting point of the two sides inside the ring shape.
In a semiconductor device according to the fourth aspect of the present invention, the shape of the element region may be square-like ring.
In a semiconductor device according to the fourth aspect of the present invention, the shape of the element region may be rectangle-like ring.
In a semiconductor device according to the fourth aspect of the present invention, the element isolation region may have a LOCOS structure.
In a semiconductor device according to the fourth aspect of the present invention, the element isolation region may have an STI structure.
In a semiconductor device according to the fourth aspect of the present invention, the conductive film may be an electrode of a MOS capacitor.
In a semiconductor device according to the fourth aspect of the present invention, the conductive film may be a gate electrode of a MOSFET.
In a semiconductor device according to the fourth aspect of the present invention, the element regions may be arranged in a matrix form.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.